1. Field of the Invention
The invention relates to an integrated circuit having a circuit block in which power supply is controlled by a waiting operation or the like.
2. Related Background Art
In conventional integrated circuit having a circuit block in which power supply is controlled by a waiting operation, when the input circuit of second circuit block inputs a signal output from first circuit block whose power supply has been broken, the input signal is put in a floating state. Thus, penetrating electricity occurred. Because of this, there is a problem that consumption electricity increased, so it is necessary to tackle this problem.
FIG. 2 is a block diagram showing a conventional integrated circuit processed by floating countermeasure of input signal.
The integrated circuit comprises a circuit block 10 in which a power supply is controlled, and a circuit block 20 in which a power supply is always supplied.
On one hand, the circuit block 10 has a logical circuit 11 that operates when the power supply is VDD1, and an inverter 12. The logical circuit 11 has a function to output signals SIG1˜SIGn serving as data towards the circuit block 20, and a control signal CON used for notifying of a breaking of the power supply just before the power supply is broken. The inverter 12 has a MOS transistor 12a with P channel (hereinafter: PMOS) and a MOS transistor 12b with N channel (hereinafter: NMOS). The PMOS and the NMOS are connecting in series each other. Then, the inverter inputs the control signal CON, and inverts the control signal CON, further output the signal inverted as a mask signal MASK.
On the other hand, the circuit block 20 has logical product gates (with respect to each, hereinafter: AND) 211˜21n whose first input terminals receive the signals SIG1˜SIGn respectively, and a logical circuit 22 receiving output signals respectively output from the ANDs 211˜21n. Further, the circuit block 20 has a node N1 receiving the mask signal MASK from the circuit block 10. At the node N1, while a latch circuit 23 formed from two inverters 23a and 23b mutually connecting in a loop is jointed, second input terminals of the ANDs 211˜21n are jointed. Otherwise, the output impedance of the latch circuit 23 is set and is sufficiently bigger than that of the inverter 12 in the circuit block 10.
In such integrated circuit, when supplying the circuit block 10 with a effective power supply VDD1, the control signal CON is set at low level “L”, then the mask signal MASK becomes high level “H”. Thus, because the node N1 receives the mask signal MASK, the node N1 becomes “H” and the latch circuit 23 is kept in “H” level by compulsion. In this case, these signals SIG1˜SIGn output from the logical circuit 11 are transferred to the logical circuit 22 through these ANDs 211˜S21n.
Next, as a preparation for breaking the power supply of the circuit block 10, in the state that the effective voltage VDD1 of the power supply is being supplied, the control signal CON changes into “H”. Thus, the mask signal MASK becomes “L”. Because of this, the node N1 becomes “L” and the latch circuit 23 is kept in “L” level by compulsion. In this case, all the ANDs 211˜S21n output signals indicating “L” level.
Then, the voltage VDD1 of the power supply of the circuit block 10 is broken. The output side of the inverter 12 in the circuit block 10 is put in high-impedance state. However, because the latch circuit 23 outputs “L” signal to the node N1 so that the logical circuit 22 still receives signals all indicating “L”, the input side of the logical circuit 22 does not become high-impedance state.
Moreover, with respect to the circuit block 10, when the voltage VDD1 of the power supply is supplied again, by operations such as reset or the like, the mask signal MASK fixed in “L” state is changed into “H”. Thus, the latch circuit 23 in the circuit block 20 is set in “H” level by compulsion again, so these signals SIG1˜SIGn output from the logical circuit 11 can be transferred to the logical circuit 22 through these ANDs 211˜S21n.
However, in such conventional integrated circuit, there are the following problems.
(1) The mask signal MASK, when the power supply of the circuit block 10 is broken completely, becomes high-impedance state. But during the voltage VDD1 drops completely from a operation-guaranteeing value to 0V, the mask signal MASK maybe makes the latch circuit 23 keep “H”. Thus, even if the power supply has been broken, the node N1 maybe keeps in “H” level. Because of this, the logical circuit 22 in the circuit block 20 will receive some unstable signal, so that penetrating electricity increases.
(2) In the state that the power supply was broken, if some noise is mixed in the mask signal MASK, the unstable signals SIG1˜SIGn will enter the logical circuit 22, so that penetrating electricity occurs.
(3) When the mask signal MASK changes, the signal on the node N1, because conflicting with the output signal of the latch circuit 23, changes behind the changing time of the mask signal MASK. Thereby, if the mask signal MASK is not used for mask control, with respect to the node N1, it is impossible to obtain a correct time.
(4) In general, in order to judge the quality of an integrated circuit, a scan test is performed. In such scan test, though the power supply is being supplied, the mask signal MASK output from the circuit block 10 changes into “L” or “H”. When the mask signal MASK becomes “L”, all the ANDs 211˜21n in the circuit block 20 becomes off, so that the signal SIG1˜SIGn output from the circuit block 10 could not enter the logical circuit 22. Thus, the scan test could not be performed completely.
(5) While the power supply of the circuit block 10 is supplied again and its voltage VDD1 rises to an operation guaranteeing value from 0V, even if fixedly setting the mask signal MASK at “L” level by reset operation or the like, the “L” level of the mask signal MASK can not be guaranteed. Because of this, if only the node N1 receives a “H” signal for an instant, the latch circuit 23 will keep the “H” level, so that the node N1 is set by “H”. Thus, the unstable signals SIG1˜SIGn of the circuit block 10 will enter the logical circuit 22 results in wrong operation.